1. Field of the Invention
The present invention relates to a bootstrap circuit and the like, which are preferable for a driving circuit of a display device such as a liquid crystal display device, an organic EL display device, etc.
2. Description of the Related Art
Recently, there has been a wide spread of an active-matrix type display device having thin-film transistors as active elements integrated on each pixel. Particularly, an active-type liquid crystal device using polysilicon transistors has become popular for portable devices such as a portable telephone and the like, since it allows size reduction of the device. The polysilicon thin-film transistor exhibits higher mobility than that of an amorphous silicon thin-film transistor. Therefore, not only pixel transistors for constituting the pixels but also the driving circuit can be formed easily in the periphery of the pixel unit by the same manufacture process. As the driving circuits, there are a gate-line driving circuit and a source-line driving circuit for driving, respectively, a plurality of scanning lines (gate lines) and a plurality of signal lines (source lines) which are orthogonal to each other. For the gate-line driving circuit and the source-line driving circuit, a scanning circuit constituted with a plurality of shift registers is used.
For the shift register constituting such scanning circuit, in general, there is used a CMOS circuit in which N-channel type transistor and P-channel type transistors are combined.
However, there is such a shortcoming in the manufacture process of the CMOS that there requires a great number of steps in the process for fabricating both the N-channel type transistors and the P-channel type transistors.
Thus, there has been proposed a circuit (single-conductive-type transistor) that is constituted with only either the P-channel type or the N-channel type conductive transistors for cutting the manufacture cost through shortening the manufacture process than the case of the CMOS.
FIG. 28 shows a scanning circuit using conventional shift registers disclosed in JP Patent No. 2921510. The scanning circuit is constituted with a plurality of shift registers, however, FIG. 28 illustrates two shift registers, n-th and (n+1)-th registers, by way of example, in which an output signal OUT of the (n−1)-th stage is inputted to an input IN of the shift register of the n-th stage, and an output signal OUT of the n-th stage is inputted to an input IN of the shift register of the (n+1)-th stage, respectively. Further, although not shown, a start signal inputted from outside is inputted to the shift register of the first stage.
The conventional shift register shown in FIG. 28 is constituted with six N-channel type transistors, Tr101, Tr102, Tr103, Tr104, Tr105, Tr106, and Tr111, Tr112, Tr113, Tr114, Tr115, Tr116, which is formed to output, by shifting the phase, the input signal IN inputted to each of the signal-input transistors Tr101 and Tr111.
Therefore, by connecting a plurality of shift registers in series, it is possible to form a scanning circuit that outputs the start signals whose phases are shifted in order.
FIG. 29 is a timing chart for showing action of the conventional shift register shown in FIG. 28. Referring to FIG. 28 and FIG. 29, the action of the circuit will be described.
First, when the output signal OUT of the (n−1)-th stage, i.e. the input signal IN of the n-th stage, becomes high level at time t1, the transistor Tr101 becomes conductive. Thus, Vdd-Vt voltage is set at a node N101 between the transistor Tr101 and the transistor Tr102, and the voltage is held in a holding capacitor C101. VDD is a supply voltage, and Vt is a threshold voltage of the transistor Tr101. In that state, the transistor Tr104 also becomes conductive. However, a clock signal CL1 is low level so that the output signal OUT_n maintains the low level. Furthermore, although the transistor Tr106 becomes conductive, node N102 stays at low level since the output signal OUT_n is low level.
Then, when the input IN changes from the high level to the low level at a timing of time t2, the transistor Tr101 becomes nonconductive and the node N101 comes in a floating state. In that state, the clock signal CL1 also changes from the low level to the high level. Thus, the potential of the node N101 is boosted up to a higher voltage than Vdd-Vt due to the bootstrap effect through the holding capacitor C101, and the gate-drain capacity and gate-source capacity of the transistor Tr104. Therefore, sufficient voltage is applied between the gate and the source of the transistor Tr104, so that a high-level clock signal CL1 flows into the transistor Tr104, thereby boosting up the output signal OUT_n to high level. Furthermore, the transistor Tr106 in that state is also conductive. Therefore, the high-level clock signal CL1 flows through the transistor Tr104 and Tr106, and the node N102 becomes high level as well.
At the next timing of time t3, the output signal OUT_n+1 of the (n+1)-th stage changes to high level so that the transistors Tr102, Tr103 are made conductive, thereby bringing the node N101 to low level. In that state, the transistor Tr105 also becomes conductive by the clock signal CL2 so that the output signal OUT_n also becomes low level. As a result, the voltage held in the holding capacitor C101 becomes zero.
At the next timing of time t4, the clock signal CL1 becomes high level. However, the output signal OUT_n stays at low level by keeping the transistor Tr104 to be nonconductive through maintaining the holding capacitor C101 to have a larger value than the gate-drain capacitor C102 of the transistor Tr104.
At the timing of time t5 and thereafter, the transistor Tr105 becomes conductive when the clock signal CL2 is high level and maintains the output OUT_n to low level. When the clock signal CL1 is high level, the holding capacitor C101 is maintained to have a large value for maintaining the transistor Tr104 to be nonconductive, so that the output signal OUT_n stays at low level.
Through the action described above, there is obtained the output signal OUT_n that is the output signal of the (n−1)-th stage whose phase is shifted by a half the cycle of the clock signals CL1 and CL2.
For the (n+1)-th stage, each of the transistors Tr111-Tr116 functions in the same manner as each of the transistors Tr101-Tr106. Thus, the output signal OUT_n+1 can be obtained by the same operation principle as that of the n-th stage. However, as shown in FIG. 28, connection of the clock signals CL1 and CL2 for the (n+1)-th stage is reversed from that of the n-th stage for allowing the same action. That is, by changing connection between the clock signals CL1 and CL2 for the even-number stages and the odd-number stages, there are obtained the outputs whose phases are shifted in order.
Considering the case where this shift register is applied to the scanning circuit for driving the gate lines of a liquid crystal display device, it is necessary to increase the driving capacity by extending channel width of the transistors Tr104 and Tr105, since a large gate-line load is connected to the output end OUT. Normally, these are set to have the channel width larger by one digit or more compared to that of the transistors Tr101-103 and 106, so that the size of the transistor becomes larger. When the channel width of the transistors Tr104 and 105 is extended, the capacity of the holding capacitor C101 needs to be increased proportionally. Thus, the holding capacitor C101 needs to have a large area. If the holding capacitor C101 is small, the gate voltage of the transistor Tr104 is boosted up by the gate-drain capacitor C102 of the transistor Tr104 when the clock signal CL1 changes from low level to high level. As a result, the transistor Tr104 becomes conductive. When the transistor Tr104 is made conductive, a high-level clock signal CL1 is outputted as the output signal OUT_n.
FIG. 28 shows the case where the conventional shift register is constituted with the N-channel type transistors. However, it can also be constituted with the P-channel type transistors. FIG. 30 is a block diagram of a circuit when constituted with the P-channel type transistors, and FIG. 31 is a timing chart of the circuit shown in FIG. 30. As shown in FIG. 31, a large difference when using the P-channel type transistors is that the polarity of the waveform is inverted with respect to that of the timing chart shown in FIG. 29.
Furthermore, Japanese Unexamined Patent Publication 2003-16794 also discloses another example where a shift register is constituted with the N-channel type transistors.
FIG. 32 is a circuit block diagram of the shift register disclosed in Japanese Unexamined Patent Publication 2003-16794, and FIG. 33 is a timing chart for showing the action of the shift register.
In the circuit shown in FIG. 32, the gate voltage (F-point) of a transistor 22 is generated by a transistor 34 and a transistor 33. With this, as shown in the timing chart of FIG. 33, potential of the F-point becomes high level from time t2 to t0 and the transistor 22 is made conductive. Thus, potential of A-point during this period becomes low level, which allows a transistor 24 to be nonconductive. Therefore, it is possible to make the transistor 24 nonconductive during that period without the holding capacitor C101 that is provided in the circuit shown in FIG. 28.
In this structure, however, there is an electric current flown through a positive power source DD terminal, transistor 26, transistor 23, and negative power source SS terminal, when the potential of the A-point during the period of the time t0-t2 is high level.
Therefore, the electric power for this electric current is a factor for increasing the power consumption even though there requires no power consumed for charging and discharging the holding capacitor C101. Furthermore, the voltage of the A-point during the time t1-t2 becomes higher than the positive power source DD voltage due to the bootstrap effect. Thus, a voltage that is higher than the supply voltage is applied between the drains and sources of the transistor 21 and the transistor 22.
In the liquid crystal display device to which such scanning circuit is mounted, the resolution of the screen has been dramatically improved recently. In accordance with this, there has also been desired a circuit that allows size reduction of the scanning circuit.
However, in the conventional shift register disclosed in JP Patent No. 2921510, it is necessary to connect the holding capacitor C101 between the gate and the source of the transistor Tr104, which is still larger than the gate-drain capacitor C102 of the transistor Tr104 with the large channel width.
The circuit area becomes large as a result and it is difficult to downsize the circuit. Further, the power consumption is increased for charging and discharging the holding capacitor C101 that has the large capacity.
With the shift register disclosed in Japanese Unexamined Patent Publication 2003-16794, it is not necessary to form a holding capacitor. However, an electric current is flown from the positive power source (DD terminal) to the negative power source (SS terminal) through the transistors 26 and 23, thereby increasing the power consumption like the above-described conventional case. Furthermore, the voltage of the A-point becomes higher than the positive power source DD voltage due to the bootstrap effect. Thus, the voltage higher than the supply voltage is applied between the drain and source of the transistors 21 and 22, thereby facing deterioration in the reliability of the transistor.
Furthermore, since the output is used as the input of the next stage in the conventional shift register, the voltage amplitude of the output signal is deteriorated when the transistor characteristic fluctuates (the driving capacity is decreased). As a result, in the scanning circuit constituted with the conventional shift registers, attenuation of the output amplitude increases from the earlier stage to the subsequent-stages. At last, it comes to a state where no shift action can be performed.